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- Newsgroups: comp.lang.c
- Path: ritz.mordor.com!news
- From: benjamin@ritz.mordor.com (Joseph Thomas)
- Subject: Help: Need to simplify a Makefile for a large project
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- Sender: benjamin@ritz.mordor.com
- Organization: None
- Message-ID: <5rg2d4ti39.fsf@ritz.mordor.com>
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- Date: Thu, 25 Jan 1996 15:22:18 GMT
-
- I'm trying to devise an efficient method of constructing a Makefile
- for a big project that needs to function like this:
-
- (oversimplified example):
-
-
- APP_1_DEFINE = -D APP_1
- APP_2_DEFINE = -D APP_2
-
- all: project1 project2
-
- project1: a.c b.c
- cc $(APP_1_DEFINE) project.c a.o b.o -o project1
-
- a: a.c
- cc -c $(APP_1_DEFINE) a.c -o a.o
-
- b: b.c b.h
- cc -c $(APP_1_DEFINE) b.c -o b.o
-
-
- project2: a.c b.c
- cc $(APP_2_DEFINE) project.c a.o b.o -o project2
-
- a: a.c
- cc -c $(APP_2_DEFINE) a.c -o a.o
-
- b: b.c b.h
- cc -c $(APP_2_DEFINE) b.c -o b.o
-
-
-
- (This example itself is probably incorrect because I'm making a and b
- a target twice, but I'm hoping it will get my idea across anyway).
-
- In other words, every time a dependent file changes, I need to make
- two 'versions' of the whole project. All the differences between
- project1 and project2 come about strictly because of the -D APP_#
- being passed to the compiler.
-
- Isn't there some way to do this without having to duplicate one
- version's definition? Is it possible to have the
-
- project1: a.c b.c
-
- line look something like
-
- project$(VERSION): a.c b.c
-
- , where, in this example, VERSION would be 1, then 2, and have make
- "loop" through the definition of project for the two different
- versions? Even better, could the -D APP_#_DEFINE also be derived from
- VERSION? (for each iteration, APP_DEFINE's value could change to
- APP_$(VERSION) ) - thus requiring me to add only one extra value of
- VERSION to the Makefile everytime I want to introduce a new version of
- the project?
-
- Help would be greatly appreciated
- -Joe
-